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COATING THICKNESS GAGES
Coating thickness or dry film thickness (DFT) is an important variable that plays a role in product quality, process control, and cost control. Measurement of film thickness can be accomplished by selecting the best mil gage for the particular application.
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DFT Testability Analysis Software
Landrex Technologies Co., Ltd.
DFT Testability Analysis Software
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DFT Validation And Silicon Debug Platform
NEBULA Silicon Debugger
NEBULA provides advanced features for performing early validation of DFT infrastructure and ATPG patterns in first silicon. The NEBULA solution directly imports test pattern formats and DFT information from leading EDA vendor tools, such as Synopsys' TetraMAX and Cadence's Encounter Test.
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Electrical DfT & Fault Coverage Analyzer
TestWay
TestWay's electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.
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Framework for Soft-Error Protection
RobustScan™
RobustScan™ provides a platform for users to pick patented Configurable Soft-Error Resilience (CSER) cells or their preferred SER mitigation cells. First, Soft-Error Rate (SER) analysis is performed. Then it performs automatic robust-scan-cell and hardenedcombinational- cell selection and synthesis. Finally it generates verification testbenches for the final design. RobustScan™ can be used with scan chains inserted using third-party tools; it can be linked to third-party�s SER analysis programs and is fully compatible with SynTest�s existing DFT tools for test, debug, and diagnosis.
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Impedance/Game-Phase Analyzers
A/D converted input signals undergo discrete Fourier transform (DFT) to calculate complex impedance values and obtain parameters and characteristics specific to the DUT, such as its capacitance, inductance and quality factor. Original NF algorithms are also applied to allow equivalent circuits made up of R, L and C along with the constants for those circuits to be estimated from the complex impedance spectrum obtained by sweeping the frequencies.
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Integration Tool Suite
TurboDFT
TurboDFT contains a suite of very useful and powerful DFT integration tools. TurboDFT allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors
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Phase Meter
SD1000
The SD1000 phase meter offers superb accuracy with a wide range of signal conditions. Conventional phase meters are easily upset when small levels of noise and distortion are present - the result is often unstable and incorrect phase readings. The SD1000 overcomes this by using Discrete Fourier Analysis (DFT), this process rejects any noise and distortion without the need for tracking filters.
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ScanWorks IJTAG Test
ScanWorks IJTAG Test
The ScanWorks Internal JTAG (IJTAG) tools allow system-on-a-chip (SoC) designers, DFT engineers and validation engineers a new and simpler way to access, control and run any embedded instrument designed into chips. When the IEEE ratifies the IEEE 1687 IJTAG standard in 2013, it will enable easy access to run any functional type of IJTAG instrument. ASSET is the first tool supplier with development tools available today for the early adopters of this important new technology.
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Transistor-Level Defect Simulator
Tessent DefectSim
Tessent DefectSim is a transistor-level defect simulator for analog, mixed-signal (AMS), and non-scan digital circuits. It measures defect coverage and defect tolerance. Tessent DefectSim is perfect for both high-volume and high-reliability ICs. Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT. Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect.
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A Comprehensive Package of DFT Tools
DFT- PRO Plus
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow
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ASIC / COT / FPGA Design
EL & Associates, Inc. specializes in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. We engage with customers from RTL phase to silicon prototype. The ELA methodology is optimized to manage risk in design, manufacture and product deployment. ELA has successfully completed over 750 designs to date.
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Prototyping & Test Consulting Services Solutions
Don’t cut corners on the path to quality. We are experts in Design for Test (DFT), Design for Manufacturing (DFM), agile development, prototyping and standards/best practices in many industries. Speak to our prototyping and consulting services experts to ensure you make the right decisions and investments at the start of your project.
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DFT Consulting
SiliconAid Solutions provides expert consulting services for all aspects of semiconductor Design-for-Test (DFT) development and implementation. Staffed by experts with proven track records from major semiconductor manufacturers, SiliconAid focused expertise provides you resources when and where you need them the most.
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Design for Testability (DFT Test)
Corelis can provide you with design consultation and an analysis of your design for boundary-scan testability. We will review your design and make specific recommendations that if implemented will improve the testability. We can also suggest improvements that will increase test coverage and allow boundary-scan to be implemented in a more cost-effective manner.This service also includes a DFT test coverage analysis that we recommend to do after schematic capture and before PCB layout. At this stage of product development, Corelis provides you with a comprehensive test coverage reports that identifies all of the boundary-scan nets and pins and classifies them as completely tested, partially tested, or not tested. The report also recommends where to add test points (pads) for physical “nails” access if additional test coverage is required.
