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Boundary Scan
PROGBSDL
PROGBSDL software converts a BSDL file for an unprogrammed PLD into a BSDL file with the same pin usage as the programmed PLD.
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BSDL models for Verilog, LASAR, HILO
MODBSDL
MODBSDL Software reads a BSDL file and writes an ACUGEN-format simulation model. This model can then be simulated and fault graded using ACUGEN's ATGEN product, or converted to another simulation format.
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Boundary Scan Software
ACUTAP Toolkit
The ACUTAP Toolkit is a handy collection of tools for reading, writing, modifying, checking, testing and working with BSDL files and boundary scan testing situations.
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Boundary Scan
TurboBSD
TurboBSD is SynTest high-performance Boundary Scan Designer. It is 100% compliant to the IEEE 1149.1 Boundary Scan Standard. TurboBSD performs Boundary Scan logic synthesis, creates BSDL (Boundary Scan Description Language) file, and generates Boundary Scan test patterns
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Develop - Simulate - Validate JTAG / IJTAG based IP
NEBULA
You, your vendors and your customers being able to use one common interface to control and observe on-chip IP, resources and instruments. The figure below shows an example IC. The new IEEE 1149.1-2013 standard supports an init-data register for configuring the analog paramaters of I/O as well as controlling on-chip PLLs. The standard further extends this by defining in BSDL user test data registers or 'scan chains'. These registers enable the ability of generic software to control and observe mission mode IP and instruments simply by describing the register interface in BSDL.
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BSDL File Validation
Corelis offers services to validate the accuracy of Boundary-Scan Description Language (BSDL) files that characterize the boundary-scan functionality of semiconductor devices. These services include validation of a device's BSDL file while the chip is still in development and BSDL file accuracy verification against actual silicon.