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RTL
Resisitor-transistor logic.
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Development Of Custom RTL Design Applications
Defacto’s STAR is also an application development environment for CAD Teams to develop in-house and custom RTL applications. It allows multi-APIs access to “RTL Build & Signoff” capabilities with higher flexibility beyond Tcl.
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Embedded Development Kit
TySOM
The TySOM Embedded Development Kit is for the embedded designer who needs a high-performance RTL simulator/debugger for their embedded applications such as IoT, Factory Automation, UAV and Automotive. The kit includes Riviera-PRO Advanced Verification Platform and a Xilinx Zynq development board that contains single Zynq chip (FPGA + Dual ARM Cortex-A9), memories (DDR3, uSD), communication interfaces (miniPCIe, Ethernet, USB, Pmod, JTAG) and multimedia interfaces (HDMI, audio, CMOS camera).
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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Hybrid Verification Platform
HES-DVM
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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PowerPro RTL Low-Power
The PowerPro RTL Low-Power Platform provides a complete solution to accurately measure, interactively explore and thoroughly optimize power during the RTL development cycle.
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RTL Lint Analyzer and Rule Checker
Ascent Lint
Ascent Lint is a state-of-the-art RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.
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SoC Integration At RTL
Before logic synthesis, STAR enables full implementation capabilities towards IP and connectivity insertion with a real-time monitoring of the integration progress. This enables SoC creation in minutes and maximize design reuse from existing projects.
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SoC Signoff & Structural Verification
Defacto’s STAR augments existing RTL verification flows by providing fully automated structural checks. Users can also define and build their custom checks.
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Widgets - Automatic Schematic Generation
Nlview
Concept Engineering's Nlview engine provides automatic generation of schematic diagrams for different levels of electronic circuits, including gate-level, RTL and block-level. Optional engines are available for the system-level (S-engine) and for the transistor-level (T-engine). The schematic layout can be modified and controlled by human intervention and always optimized by algorithms. A fine granularity of user preferences can be mixed with machine computed "beauty" to get the best human readable diagrams. Interactive circuit exploration is supported by incremental schematic generation technology. Nlview provides a set of APIs and interfaces with a certain GUI environment. Please see also the Nlview Widgets datasheet (PDF file).
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RTL Floorplanner, Partitioning, And Floorplan Verification
ConStruct
ConStruct is an early RTL Floorplanner, partition explorer, and floorplan verification tool. It can further be used to generate the partitioned RTL based on specified criteria.
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A Comprehensive Package of DFT Tools
DFT- PRO Plus
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow
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Advanced Multimode Sign-off Verification
Verix PhyCDC
Verix PhyCDC is the only solution that delivers precise netlist CDC sign-off including glitch checking. RTL CDC sign-off assumptions may become invalid because of logic synthesis and power optimizations. Verix PhyCDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains are CDC-safe at the gate level. Complementing Real Intent’s Verix CDC solution that provides comprehensive analysis for RTL sign-off, Verix PhyCDC delivers the most advanced netlist sign-off for giga-gate designs.
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Analyze RTL
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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ASIC / COT / FPGA Design
EL & Associates, Inc. specializes in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. We engage with customers from RTL phase to silicon prototype. The ELA methodology is optimized to manage risk in design, manufacture and product deployment. ELA has successfully completed over 750 designs to date.
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RTL debugger and viewer for Verilog and VHDL
RTLvision
RTLvision PRO provides easy RTL debugging and fast visualization of RTL code, so that engineers can easily understand, implement and optimize VHDL, Verilog or SystemVerilog code. Please check out the Demo Videos: Basic Features and Clock Tree Analyzer.
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Static Design Verification
ALINT-PRO
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
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X-Design and Verification System
Ascent XV
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
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360 EC-FPGA
Functional correctness of FPGA synthesis from RTL code to final netlist. Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.
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360 EC-ASIC
ASIC synthesis verification from RTL code to final netlist.Systematic design errors, introduced by automated design refinement tools, such as ASIC synthesis, can be hard to detect, and damaging if they make it into the final device. Formal Equivalency Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized code.
