Excellicon Inc.
Excellicon patented software is designed by semiconductor professionals for semiconductor professionals with the designer point of view in mind. The company products provides a new and innovative approach to compile and generate constraints correct by construction as a direct contrast to out dated trial and error approach practiced in the industry.
- 1 949-200-8477
- info@excellicon.com
- 23152 Verdugo Dr.
Ste-106
Laguna Hills, CA 92653
United States
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Applications
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product
A Visual And Interactive Tool For Pre-CTS Analysis And Post-CTS Verification
ConTree
ConTree is a clocking logic visualization, analysis and verification tool. It is used for both pre-CTS clocking analysis as well as post-CTS clock tree verification.
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RTL Floorplanner, Partitioning, And Floorplan Verification
ConStruct
ConStruct is an early RTL Floorplanner, partition explorer, and floorplan verification tool. It can further be used to generate the partitioned RTL based on specified criteria.
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Constraints Certifier Platform
ConCert
ConCert is a sign-off platform providing a unique system for verification, demotion and budgeting of timing constraints at any stage of the ASIC or FPGA flow.
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Automatic Constraints Compiler & Manager
ConMan
ConMan is the first commercially available formal constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling and managing sign-off quality correct-by-construction timing constraints for all applications.
